Division-based versus general decomposition-based multiple-level logic synthesis

During the last decade, many different approaches have been proposed to solve the multiple-level synthesis problem with different minimum functionally complete systems of primitive logic blocks. The most popular of them is the division-based approach. However, modem microelectronic technology provides a large variety of building blocks which considerably differ from those typically considered. The traditional methods are therefore not suitable for synthesis with many modem building blocks. Furthermore, they often fail to find global optima for complex designs and leave unconsidered some important design aspects. Some of their weaknesses can be eliminated without leaving the paradigm they are based on, other ones are more fundamental. A paradigm which enables efficient exploitation of the opportunities created by the microelectronic technology is the general decomposition paradigm. The aim of this paper is to analyze and compare the general decomposition approach and the division-based approach. The most important advantages of the general decomposition approach are its generality (any network of any building blocks can be considered) and totality (all important design aspects can be considered) as well as handling the incompletely specified functions in a natural way. In many cases, the general decomposition approach gives much better results than the traditional approaches

Decomposition logic synthesis approach for look up table FPGAs

In this paper, a technology driven logic synthesis approach for look up table FPGAs is presented. Decomposition and bottom-up construction are the key concepts of this approach. By using functionally complete compact modeling with set systems, technology mapping is trivial. The method offers correctness by construction and easy post-synthesis verification and uses a multiple criteria search algorithm for constructing near optimal solutions.</p

Decomposition logic synthesis approach for look up table FPGAs

In this paper, a technology driven logic synthesis approach for look up table FPGAs is presented. Decomposition and bottom-up construction are the key concepts of this approach. By using functionally complete compact modeling with set systems, technology mapping is trivial. The method offers correctness by construction and easy post-synthesis verification and uses a multiple criteria search algorithm for constructing near optimal solutions.</p